SEL_EXT=FRAC_ENABLED, CLK_SEL=32_KHZ_OSCILLATOR, AUTOBLOCK=DISABLED, BYPASS=CCO_CLOCK_SENT_TO_PO, PD=PLL0_ENABLED, MOD_PD=ENABLED
PLL0AUDIO control register
| PD | PLL0 power down 0 (PLL0_ENABLED): PLL0 enabled 1 (PLL0_POWERED_DOWN): PLL0 powered down |
| BYPASS | Input clock bypass control 0 (CCO_CLOCK_SENT_TO_PO): CCO clock sent to post-dividers. Use this in normal operation. 1 (PLL0_INPUT_CLOCK_SEN): PLL0 input clock sent to post-dividers (default). |
| DIRECTI | PLL0 direct input |
| DIRECTO | PLL0 direct output |
| CLKEN | PLL0 clock enable |
| RESERVED | Reserved |
| FRM | Free running mode |
| RESERVED | Reserved |
| RESERVED | Reserved. Reads as zero. Do not write one to this register. |
| RESERVED | Reserved. Reads as zero. Do not write one to this register. |
| RESERVED | Reserved. Reads as zero. Do not write one to this register. |
| AUTOBLOCK | Block clock automatically during frequency change 0 (DISABLED): Disabled. Autoblocking disabled 1 (ENABLED): Enabled. Autoblocking enabled |
| PLLFRACT_REQ | Fractional PLL word write request. Set this bit to 1 if the fractional divider is enabled in the SEL_EXT bit. |
| SEL_EXT | Select fractional divider. 0 (FRAC_ENABLED): FRAC Enabled. Enable fractional divider. 1 (MDEC_ENABLED): MDEC enabled. Fractional divider not used. |
| MOD_PD | Sigma-Delta modulator power-down 0 (ENABLED): Enabled. Sigma-Delta modulator enabled 1 (DISABLED): Disabled. Sigma-Delta modulator powered down |
| RESERVED | Reserved |
| CLK_SEL | Clock source selection. All other values are reserved. 0 (32_KHZ_OSCILLATOR): 32 kHz oscillator 1 (IRC_DEFAULT): IRC (default) 2 (ENET_RX_CLK): ENET_RX_CLK 3 (ENET_TX_CLK): ENET_TX_CLK 4 (GP_CLKIN): GP_CLKIN 6 (CRYSTAL_OSCILLATOR): Crystal oscillator 9 (PLL1): PLL1 12 (IDIVA): IDIVA 13 (IDIVB): IDIVB 14 (IDIVC): IDIVC 15 (IDIVD): IDIVD 16 (IDIVE): IDIVE |
| RESERVED | Reserved |